Avalon-st sink bfm, Timing, Avalon-st sink bfm -1 – Altera Avalon Verification IP Suite User Manual
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Avalon-ST Sink BFM
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The Avalon-ST Sink BFM implements the Avalon-ST interface protocol. The Avalon-ST protocol is
point-to-point, packet oriented, and drives unidirectional data. This BFM component also includes a
procedural interface to respond to the DUT that includes an Avalon-ST source interface. The following
figure shows the top-level modules for testbench that uses the Avalon-ST Sink BFM to verify an Avalon-ST
source device. In addition to the Altera-provided Avalon-ST Sink BFM component, the testbench includes
a test program and the DUT.
The BFMs allow illegal transactions so that you can test the error-handling functionality of your
DUT. Consequently, the BFMs cannot be relied upon to guarantee protocol compliance. The Avalon
Monitor components verify protocol compliance.
Note:
Figure 9-1: Top-Level Module to Verify an Avalon-ST Source Device
Avalon-ST
Sink BFM
Test Program
Testbench
Verilog API
Avalon-ST
DUT
Avalon-ST
Source
Related Information
Timing
The following figure illustrates the timing for an Avalon-ST Sink BFM when it is ready to receive data from
an Avalon-ST source. In the first instance, the sink is not ready when the source has data. In the second
instance, the sink is ready but the source does not initially have valid data.
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