Altera Avalon Verification IP Suite - Manual (Page 213)

The Qsys Generate window displays informational messages as it generates the testbench.
d. Close the Generate window.
4. Start the ModelSim
®
simulator.
5. To run the simulation, type the following command in your working directory:
do run_simulation.tcl
This command compiles all the required HDL files, elaborates, and runs the simulation.
Example 17-1: Timing for a Write Burst with a Burst Count of Four
tb.clk
tb.reset
mstr_.avm_address[11:0]
mstr_.avm_burstcount[3:0]
mstr_.avm_waitrequest
mstr_.avm_write
mstr_.avm_writedata[31:0]
mstr_.avm_byteenable[3:0]
mstr_.avm_read
mstr_.avm_readdatavalid
slv.avs_waitrequest
slv_.avs_write
slv_.avs_read
slv_.avs_readdatavalid
slv_.avs_readdata[31:0]
mstr.avm_readdata[31:0][31:0]
slv_.avs_address[11:0]
slv_.avs_burstcount[3:0]
slv_.avs_writedata[31:0]
slv_.avs_byteenable[3:0]
80C
4
359FDD6B EAA62AD5 81174A02 0EFFE91D E7C572CF
F F F
80C
4
359FDD6B EAA62AD5 81174A02 0EFFE91D E7C572CF
F F F
Figure 17-2: Timing for a Read with Burst Count of Three
tb.clk
tb.reset
mstr_.avm_address[11:0]
mstr_.avm_burstcount[3:0]
mstr_.avm_waitrequest
mstr_.avm_write
mstr_.avm_writedata[31:0]
mstr_.avm_byteenable[3:0]
mstr_.avm_read
mstr_.avm_readdatavalid
slv.avs_waitrequest
slv_.avs_write
slv_.avs_read
slv_.avs_readdatavalid
slv_.avs_readdata[31:0]
mstr.avm_readdata[31:0][31:0]
slv_.avs_address[11:0]
slv_.avs_burstcount[3:0]
slv_.avs_writedata[31:0]
slv_.avs_byteenable[3:0]
EC0 DC8 A74
3 3 7
F F F
7D3599FA 937DBC26 39961773
7D3599FA 937DBC26 39961773
EC0 DC8 A74
3 3 7
F F F
Altera Corporation Avalon-MM Verilog HDL and VHDL Testbenches
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17-3 Running the Verilog HDL Testbench for a Single Avalon-MM Master and Slave Pair