Altera Avalon Verification IP Suite - Manual (Page 131)

event_sink_ready_assert()
event_sink_ready_assert()
Prototype:
Verilog HDL: N.A.
VHDL: bfm_id
Arguments:
void
Returns:
Signals that the
ready
signal was asserted. Description:
VHDL Language support:
event_sink_ready_deassert()
event_sink_ready_deassert()
Prototype:
Verilog HDL: N.A.
VHDL:
bfm_id
Arguments:
void Returns:
Signals that the
ready
signal was deasserted. Description:
VHDL Language support:
get_transaction_channel()
get_transaction_channel()
Prototype:
Verilog HDL: None
VHDL:
channel
,
bfm_id
,
req_if(bfm_id)
Arguments:
STChannel_t Returns:
Returns the channel identifier for the most recently removed transaction. Description:
Verilog HDL, VHDL Language support:
get_transaction_data()
get_transaction_data()
Prototype:
Verilog HDL: None
VHDL:
data
,
bfm_id
,
req_if(bfm_id)
Arguments:
STData_t
Returns:
Returns the data in the most recently removed transaction. Description:
Verilog HDL, VHDL Language support:
Altera Corporation Avalon-ST Sink BFM
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9-5 event_sink_ready_assert()