Timing, Timing -2 – Altera Avalon Verification IP Suite User Manual
Page 24
Timing
The following timing diagram illustrates the sequence of events for an Avalon-MM Master BFM. The Master
BFM drives interleaved writes and reads when the
readdatavalid
signal is present. This diagram serves as
a reference for the following discussion of API and events.
Figure 5-2: Avalon-MM Master Driving Interleaved Write and Read Transactions
writedata[31:0]
D1
D3
CLK
read
transaction1
transaction2
trans3 trans4
write
T init
T init
S
ci_1
T idle
S
ci_2
S
ci_3
S
ci_4
transactionid
waitrequest
byteenable[3:0]
T wr
T wt_1
T
wt_2
T
ID_4
writeresponse
writeid
ID_1
ID_3
readdatavalid
readdata
D2
D4
T rl_1
T rl_2
S
rc_4,
S
rc_2
S
atc
readresponse
readid
ID_2
ID_4
writeresponsevalid
Twrl_1
S
rc_1
T
ID_1
T
ID_2
T
ID_3
S
rc_3
D2
D4
Avalon-MM Master BFM
Altera Corporation
Timing
5-2
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