Using the vhdl bfms, Using the vhdl bfms -10 – Altera Avalon Verification IP Suite User Manual
Page 220

Figure 17-8: Timing for a Write Burst with a Burst Count of Four
tb.clk
tb.reset
mstr1_m0_waitrequest
mstr1_m0_write
mstr1_m0_read
mstr1_m0_readdatavalid
mstr1_m0_address[12:0]
mstr1_m0_byteenable[3:0]
mstr1_m0_burstcount[3:0]
mstr1_m0_writedata[31:0]
mstr1_m0_readdata[31:0]
slv1_s0_waitrequest
slv1_s0_write
slv1_s0_read
slv1_s0_readdatavalid
slv1_s0_burstcount[3:0]
slv1_s0_address[9:0]
slv1_s0_writedata[31:0]
slv1_s0_byteenable[3:0]
slv1_s0_readdata[31:0]
01DC
F
F
F
4
0000000C
00000015
0000001B
00000017
2
1
3A3
3A4
3A5
000 .
00000019
.
F
Figure 17-9: Timing for a Read with a Burst Count of Three
tb.clk
tb.reset
mstr1_m0_waitrequest
mstr1_m0_write
mstr1_m0_read
mstr1_m0_readdatavalid
mstr1_m0_address[12:0]
mstr1_m0_byteenable[3:0]
mstr1_m0_burstcount[3:0]
mstr1_m0_writedata[31:0]
mstr1_m0_readdata[31:0]
slv1_s0_waitrequest
slv1_s0_write
slv1_s0_read
slv1_s0_readdatavalid
slv1_s0_burstcount[3:0]
slv1_s0_address[9:0]
slv1_s0_writedata[31:0]
slv1_s0_byteenable[3:0]
slv1_s0_readdata[31:0]
13F5
0BC7
F
F
3
6
0000000D
.
00000000
000 .
00000000
0006 .
00
.
000E .
00000000
000D .
00
.
0003 .
0001C.
.
3
2
7
0
0FD
0FE
000
00000000
F
0
0000000D
00
.
Using the VHDL BFMs
The Quartus II software version 13.0 and higher provides VHDL BFM support in Qsys. To use a VHDL
BFM, your test program must include the appropriate VHDL package. For example, to use the Avalon-MM
Avalon-MM Verilog HDL and VHDL Testbenches
Altera Corporation
Using the VHDL BFMs
17-10