Altera Avalon Verification IP Suite - Manual (Page 124)

set_transaction_sop()
set_transaction_sop(bit sop)
Prototype:
Verilog HDL: sop
VHDL: sop , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the status of the start of packet signal in the out-going transaction. Description:
Verilog HDL, VHDL Language support:
signal_fatal_error
signal_fatal_error
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals that a fatal error has occurred. It terminates the simulation. Description:
Verilog HDL Language support:
signal_max_transaction_queue_size
signal_max_transaction_queue_size
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void Returns:
Signals that the pending transaction queue size threshold has been exceeded. Description:
Verilog HDL Language support:
signal_min_transaction_queue_size
signal_min_transaction_queue_size
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Signals that the pending transaction queue size is below the minimum threshold. Description:
Verilog HDL Language support:
Avalon-ST Source BFM Altera Corporation
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set_transaction_sop() 8-12