Avalon-mm monitor, Avalon-mm monitor -1 – Altera Avalon Verification IP Suite User Manual
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Avalon-MM Monitor
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The Avalon-MM Monitor verifies Avalon-MM interfaces using SystemVerilog assertions. In addition, it
provides test coverage reports. The coverage reports provide the information necessary to determine when
your test vectors provide sufficient test coverage of the DUT.
The Avalon-MM Monitor is implemented in SystemVerilog and uses the SystemVerilog Assertion (SVA)
language. The SVA language is supported by the Synopsys VCS, and Mentor Graphics Questa simulators.
If you are using ModelSim, the monitor component still compiles and simulates. However, the assertion
checking is disabled.
The following figure shows a testbench that uses an Avalon-MM Monitor to test components with Avalon-
MM interfaces. The monitor’s Avalon-MM Master interface is connected to a component’s Avalon-MM
slave interface. An Avalon-MM Slave interface is connected to a component’s Avalon-MM master interface.
The test program communicates with the monitor. The test program can use the monitor’s assertion checking
and coverage groups to ensure that all legal parameter values for the DUT’s Avalon-MM interface are tested.
The Avalon-MM Monitor also includes a transaction collector feature to collect and monitor transaction
status.
Figure 7-1: Testbench Using an Avalon-MM Monitor with Avalon-MM Interfaces
Testbench
Test Program
System Verilog with VMM
generator
object
instance
generator
object
instance
generator
object
instance
configu-
ration
transactor
Avalon-MM Monitor
M
S
S
Avalon-MM
Slave BFM
Avalon-MM
Master BFM
M
Assertion
Checking
Test
Coverage
API Methods
Transaction
Collector
initial()
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