Altera Avalon Verification IP Suite - Manual (Page 64)

get_pending_write_latency_cycle()
int get__cycle()
Prototype:
Verilog HDL: None
VHDL: pending_write_latency , bfm_id , req_if(bfm_id)
Arguments:
int
Returns:
Queries the write command queue to determine the cycles needed for the Slave
BFM to complete the current write response. Description:
Verilog HDL, VHDL Language support:
get_response_queue_size()
int get_response_queue_size()
Prototype:
Verilog HDL: None
VHDL:
response_queue_size
,
bfm_id
,
req_if(bfm_id)
Arguments:
int Returns:
Queries the response queue to determine number of response descriptors pending. Description:
Verilog HDL, VHDL Language support:
vget_slave_bfm_status
bit get_slave_bfm_status
Prototype:
Verilog HDL: None
VHDL:
slave_bfm_status
,
bfm_id
,
req_if(bfm_id)
Arguments:
bit Returns:
Queries the Slave BFM component to determine when the read transaction in the
Slave BFM has reached the maximum read transactions. A return value of 1 means
that the Slave BFM can no longer accept a new read command. Description:
Verilog HDL, VHDL Language support:
Avalon-MM Slave BFM Altera Corporation
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get_pending_write_latency_cycle() 6-16