Altera Avalon Verification IP Suite - Manual (Page 155)

signal_fatal_error
signal_fatal_error Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Notifies the testbench that a fatal error has occurred in this module. Description:
Verilog HDL Language support:
signal_transaction_fifo_overflow
signal_transaction_fifo_overflow Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Notifies the testbench that the FIFO is full and further transactions are
dropped. Description:
Verilog HDL Language support:
signal_transaction_fifo_threshold
signal_transaction_fifo_threshold
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Notifies the testbench that the transaction FIFO threshold level has exceeded. Description:
Verilog HDL Language support:
signal_transaction_received
signal_transaction_received
Prototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
void
Returns:
Notifies the testbench that a transaction has been received and queued. Description:
Verilog HDL Language support:
Altera Corporation Avalon-ST Monitor
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10-19 signal_fatal_error