Running the simulation, Running the simulation -5 – Altera Avalon Verification IP Suite User Manual
Page 208
Description
Hierarchy Variables Coding Example
Sets the Qsys simulation path to the
directory that includes the ModelSim
script. You must set this path when your
ModelSim script file (
msim_setup.tcl
) and
test program are located in different
directories.
set QSYS_SIMDIR”../st_bfm_qsys_tutorial/testbench
The hierarchy variables enable the ModelSim script to complete the following tasks necessary for the
simulation:
• Source
msim_setup.tcl
.
• Use the command aliases defined in the Qsys-generated simulation script to compile the device library
files and SystemVerilog design files (
test_program.sv
and
top.sv
). These files instantiate the test program
and the Qsys-generated testbench simulation model.
The ModelSim script (
load_sim.tcl
) then uses the command alias to elaborate the top-level simulation design.
It also loads the
wave.do
file that sets up the waveform view in the ModelSim-Altera software.
Running the Simulation
In this section, you run a simulation in the ModelSim-Altera software on the testbench that you created. To
complete this simulation, use the test program provided in the design files to provide the stimulus. By default,
msim_setup.tcl
compiles the BFM source files into different libraries. In this tutorial, the BFM source files
must be in a single library.
Complete the following steps to compile the source files to a single directory:
1. In Qsys, on the Tools menu click Nios II Command Shell.
2. In Nios II Command Shell, change the directory to
.
3. Type the following command and hit enter:
ip-make-simscript --spd=st_bfm_qsys_tutorial_tb.spd --output-
directory=./st_bfm_qsys_tutorial/testbench/ --compile-to-work
4. To run the simulation, start the ModelSim-Altera software.
5. On the File menu click Change Directory.
6. Navigate to
directory, and click OK.
7. On the Compile menu, click Compile Options.
8. Click the Verilog & System Verilog tab.
9. In the Language Syntax box, select Use SystemVerilog and click OK.
10. On the File menu, click Load > Macro File.
Ensure you activate your cursor on the ModelSim-Altera Transcript window, otherwise the Load
function is disabled.
Note:
11. Select load_sim.tcl, and click Open. The Tcl file creates a new working library, compiles all source files,
runs simulation, and loads signals into the ModelSim waveform viewer.
12. To run the simulation, type the following command in the ModelSim-Altera transcript console:
run 1200 ns
You can run the
h
command to show the available options for the
msim_setup.tcl
macro script.
Note:
Altera Corporation
Avalon-ST Verilog HDL Testbench
16-5
Running the Simulation