Altera Avalon Verification IP Suite - Manual (Page 209)

Observing the Results
You can view the simulation results in the following two ways:
• In the ModelSim transcript console
• In the waveforms window
The transcript ModelSim transcript provides the following information:
• When the Avalon-ST source BFM drives a transaction, it also prints the transaction to the ModelSim
transcript window.
• The Avalon-ST Sink BFM also prints the transactions it receives on the transcript window.
• The Avalon-ST Sink BFM compares the transaction it receives with the one sent by the Avalon-ST Source
BFM. The results of the comparison are printed on the transcript window.
• The idles values for the source and sink are different:
• The Avalon-ST Source BFM sets the number of idle cycles to zero using the
set_transaction_idles
function.
• The Avalon-ST Sink BFM waits for three cycles before receiving the first transaction. The three-cycle
delay is necessary for the transaction to propagate from the input to the output of the sink FIFO buffer.
• The difference in values for the
idle
field is not an error. The Avalon-ST interface protocol allows
source and sink components to have different latencies.
The following example shows the ModelSim transcript for the source response latency. This latency is the
number of clock cycles the Avalon-ST Single-Clock FIFO buffer takes when the Avalon-ST Single-Clock
FIFO buffer backpressures the Avalon-ST Source BFM. The third response shows a non-zero response
latency. During the third transaction, the Avalon-ST Single-Clock FIFO buffer is full. It is not able to receive
the transaction. As a result, the Avalon-ST Single-Clock FIFO buffer backpressures the Avalon-ST Source
BFM.
# 1030000:INFO:top.pgm.test_threads.source_response_thread: Source response latency
0
# 1050000:INFO:top.pgm.test_threads.source_response_thread: Source response latency
0
# 1090000:INFO:top.pgm.test_threads.source_response_thread: Source response latency
1
# 1110000:INFO:top.pgm.test_threads.source_response_thread: Source response latency
0
Avalon-ST Verilog HDL Testbench Altera Corporation
Send Feedback
Observing the Results 16-6