Altera Avalon Verification IP Suite - Manual (Page 200)

set_instruction_a()
void set_instruction_a()
Prototype:
Verilog HDL: ci_addr_t address
VHDL: ci_addr_t address , bfm_id , req_if(bfm_id)
Arguments:
void
Returns:
Sets the instruction register file address
a
value. Description:
Verilog HDL, VHDL Language support:
set_instruction_b()
void set_instruction_b()
Prototype:
Verilog HDL: ci_addr_t address
VHDL:
ci_addr_t address
,
bfm_id
,
req_if(bfm_id)
Arguments:
void Returns:
Sets the instruction register file address
b
value. Description:
Verilog HDL, VHDL Language support:
set_instruction_c()
void set_instruction_c()
Prototype:
Verilog HDL:
ci_addr_t address
VHDL:
ci_addr_t address
,
bfm_id
,
req_if(bfm_id)
Arguments:
void Returns:
Sets the instruction register file address
c
value. Description:
Verilog HDL, VHDL Language support:
set_instruction_timeout()
void set_instruction_timeout()
Prototype:
Verilog HDL:
int timeout
VHDL:
int timeout
,
bfm_id
,
req_if(bfm_id)
Arguments:
void
Returns:
Sets the timeout value for an instruction. Set the value to 0 to disable timeouts. Description:
Verilog HDL, VHDL Language support:
Nios II Custom Instruction Slave BFM Altera Corporation
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set_instruction_a() 15-10