Altera Avalon Verification IP Suite - Manual (Page 13)

Verilog HDL with a few basic SystemVerilog constructs that are supported by ModelSim
®
-Altera Edition
(AE).
The Quartus II software version 13.0 and higher extends VHDL BFM support in Qsys. The VHDL BFMs
wrap the SystemVerilog implementation and include additional logic to support VDHL.
Table 1-1: BFM Language Support
VHDL Support Verilog HDL
Support
BFM
Yes Yes Clock Source and Reset Source
Version 13.0 and higher Yes Avalon Interrupt Source and Sink
Version 13.0 and higher Yes Avalon-MM Master, Slave, and Monitor
Version 13.0 and higher Yes Avalon-ST Source, Sink, and Monitor
Version 14.0 and higher Yes Conduit and Tri-State Conduit
Version 13.0 and higher Yes External Memory
Version 13.0 and higher Yes Nios II Custom Instruction Master and Slave
The VHDL BFM has four parts as shown in the figure below.
• SystemVerilog BFM—Contains the BFM implementation and behavioral model, and the SystemVerilog
API. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
• VHDL package—Provides the VHDL API used to control the BFM and interface with your test program.
The package contains VHDL procedures and events.
• API handler logic—SystemVerilog logic block that translates your test program’s VHDL API calls to
SystemVerilog API calls. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
Introduction to Avalon Verification IP Suite Altera Corporation
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BFM Implementation 1-2