Avalon-st monitor, Avalon-st monitor -1 – Altera Avalon Verification IP Suite User Manual
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Avalon-ST Monitor
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The Avalon-ST Monitor verifies Avalon-ST interfaces using SystemVerilog assertions. In addition, it provides
test coverage reports. The coverage reports provide the information necessary to determine when your test
vectors provide sufficient test coverage of the DUT.
The Avalon-ST Monitor is implemented in SystemVerilog and uses the SystemVerilog Assertion (SVA)
language. The SVA language is supported by the Synopsys VCS, and Mentor Graphics Questa. If you are
using ModelSim, the monitor component still compiles and simulates, but the assertion checking is disabled.
The following figure shows a testbench that uses an Avalon-ST Monitor to test components with Avalon-
ST interfaces. This figure illustrates that the monitor’s Avalon-ST source interface is connected to the DUT’s
Avalon-ST sink interface. An Avalon-ST sink interface is connected to the DUT’s Avalon-ST source interface.
The test program communicates with the monitor. It uses the monitor’s assertion checking and coverage
groups to assure that all legal parameter values for the DUT’s Avalon-ST interfaces are verified.
Figure 10-1: Testbench Using an Avalon-ST Monitor with Avalon-ST Interfaces
Testbench
Test Program
generator
object
instance
generator
object
instance
generator
object
instance
configu-
ration
transactor
Avalon-ST Monitor
Src
Snk
Snk
Avalon-ST
Sink BFM
Avalon-ST
Source BFM
Src
Assertion
Checking
Test
Coverage
API Methods
Transaction
Collector
initial()
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