5 watchdog wake-up, 6 power management summary, Figure 7-1. power cycle operation – Maxim Integrated High-Speed Microcontroller User Manual
Page 91
High-Speed Microcontroller User’s Guide
Rev: 062210
91 of 176
7.1.5 Watchdog Wake-Up
The watchdog wake-up is more of an application than a feature. It allows a system to enter the Idle mode
for power savings, then to wake up periodically to sample the external world. Idle mode is a low power
state
described below. Any of the programmable timers can perform this function, but the watchdog
allows a much longer period to be selected. At 12MHz, the maximum watchdog timeout is over 5.5
seconds. This contrasts with 0.78 seconds using the 16-bit timers. Software that uses the watchdog as a
wake-up alarm should only enable the watchdog interrupt and not the reset. Note that the watchdog
cannot be used to wake the system while in Stop mode since no clocks are running. Stop mode is
described below.
7.1.6 Power Management Summary
The following is a summary of the power management bits and those that are useful or related. They are
contained in the register locations
;E8h;
;91h; and
.6: Power-On Reset (POR). Hardware will set this bit on a power-up condition. Software can
read it, but must clear it manually. This bit assists software in determining the cause of a reset.
.5: Enable Power-Fail Interrupt (EPFI). Setting this bit to 1 enables the power-fail interrupt.
This will occur when V
CC
drops to approximately 4.5V, and the processor vectors to location 33h. Setting
this bit to a 0 turns off the power-fail interrupt.
.4: Power-Fail Interrupt Flag (PFI). Hardware will set this bit to a 1 when a power-fail
condition occurs. Software must clear the bit manually. Writing a 1 to this bit will force an interrupt, if
enabled.
.3: Watchdog Interrupt Flag (WDIF). If the watchdog interrupt is enabled (
will set this bit to indicate that the Watchdog Interrupt has occurred. If the interrupt is not enabled, this bit
indicates that the timeout has passed. If the watchdog reset is enabled (
clocks to strobe the watchdog prior to a reset. Software or any reset can clear this flag.
.2: Watchdog Timer-Reset Flag (WTRF). Hardware will set this bit when the watchdog timer
causes a reset. Software can read it, but must clear it manually. A power-fail reset will also clear the bit.
This bit assists software in determining the cause of a reset. If EWT = 0, the watchdog timer will have no
affect on this bit.
.1: Enable Watchdog Timer Reset (EWT). Setting this bit will turn on the watchdog timer
reset function. The interrupt will not occur unless the EWDI bit in the
register is set. A reset will
occur according to the WD1 and WD0 bits in the
register. Setting this bit to a 0 will disable the
reset but leave the timer running.
.0: Reset Watchdog Timer (RWT). This bit serves as the strobe for the watchdog function.
During the timeout period, software must set the RWT bit if the watchdog is enabled. Failing to set the
RWT will cause a reset when the timeout has elapsed. There is no need to set the RWT bit to a 0 because
it is self-clearing.
.4: Enable Watchdog Interrupt (EWDI). Setting this bit in software enables the watchdog
interrupt.