Maxim Integrated High-Speed Microcontroller - Manual (Page 106)

High-Speed Microcontroller User’s Guide
Rev: 062210 106 of 176
more details. In order for the processor to acknowledge the interrupt and vector to the ISR, the interrupt
must be enabled. Each source has an independent enable, as shown in
Table 9-A .
Prior to using any source, interrupts must be globally enabled. This is done using the EA bit at location
IE .7. Setting this bit to a logic 1 allows individual interrupts to be enabled. Setting it to a logic 0 disables
all interrupts regardless of the individual interrupt enables. The only exception is the power-fail interrupt.
This is subject to its individual enable only. The EA bit has no effect on the power-fail interrupt.
9.2 Interrupt Sources
Various combinations of interrupt sources are available on different members of the high-speed
microcontroller family. These are broken into several categories: external, timer-based, serial
communication, real-time clock, and power monitor. Each type is described below. Interrupt sources are
sampled once per machine cycle. If the source goes active after the sample, it will not be registered until
the next cycle.
9.2.1 External Interrupts
The high-speed microcontroller has six external interrupt sources. These include the standard 2 interrupts
of the 8051 architecture and four new sources. The original interrupts are INT0 and INT1. These are
active low, but can be programmed to be edge- or level-sensitive. Bits IT0 and IT1 control the detection
mode, respectively. When ITx = 0, the interrupt is triggered by a logic 0 on the appropriate interrupt pin.
The interrupt condition remains in force as long as the pin is low. When ITx = 1, the interrupt is pseudo-
edge triggered. This means that if on successive samples, the pin is high then low, the interrupt is
activated.
Since the external interrupts are sampled, the pin driver of an edge-triggered interrupt should hold both
the high condition, then the low condition for at least one machine cycles (each) to ensure detection. This
means maximum sampling frequency on any interrupt pin is 1/8 of the main oscillator frequency.
It is important to note that level-sensitive interrupts are not latched. If the interrupt is level sensitive, the
condition must be present until the processor can respond to the interrupt. This is most important if other
interrupts are being used with a higher or equal priority. If the device is currently processing another
interrupt, the condition must be present until the present interrupt is complete. This is because the level-
sensitive interrupt will not be sampled until the RETI instruction is executed.
The remaining four external interrupts are similar in nature, with two differences. First, INT2 and INT4
are active high instead of active low. Second, all of the four new interrupts are edge-detect only. They do
not have level-detect modes. All associated bits and flags operate the same and have the same polarity as
the original two. A logic 1 indicates the presence of a condition, not the logic state of the pin.
If the Power Management Modes are utilized, the designer must remember that edge triggered interrupts
must be high and low for one machine cycle before being recognized. This means that in PMM1 it will
require 128 external clock cycles to recognize a level sensitive interrupt. Similarly, in PMM2 it will
require 2048 external clock cycles to recognize a level sensitive interrupt. As a result, the interrupt
latency for these interrupts will be slightly longer in PMM1 or PMM2.