Maxim Integrated High-Speed Microcontroller - Manual (Page 14)

High-Speed Microcontroller User’s Guide
Rev: 062210 14 of 176
4. PROGRAMMING MODEL
This section provides a programmer’s overview of the high-speed microcontroller core. It includes
information on the memory map, on-chip RAM, SFRs, and instruction set. The programming model of
the high-speed microcontroller is very similar to that of the industry standard 80C52. The memory map is
identical. It uses the same instruction set, though instruction timing is improved. Several new SFRs have
been added.
4.1 Memory Organization
The high-speed microcontroller, like the 8052, uses several distant memory areas. These are registers,
program memory, and data memory. Registers serve to control on-chip peripherals and as RAM. Note
that registers (on-chip RAM) are separate from data memory. Registers are divided into three categories
including directly addressed on-chip RAM, indirectly addressed on-chip RAM, and SFRs. The program
and data memory areas are discussed in Section
4.1.1 : Memory Map. The registers are discussed in
Section 4.1.2 : Register Map.
4.1.1 Memory Map
The high-speed microcontroller uses a memory-addressing scheme that separates program memory
(ROM) from data memory (RAM). Each area is 64kB beginning at address 0000h and ending at FFFFh
as shown in
Figure 4-1 . The program and data segments can overlap since they are accessed in different
ways. Program memory is fetched by the microcontroller automatically. These addresses are never
written by software. In fact, there are no instructions that allow the ROM area to be written. There is one
instruction (MOVC) that is used to explicitly read the program area. This is commonly used to read look-
up tables. The data memory area is accessed explicitly using the MOVX instruction. This instruction
provides multiple ways of specifying the target address. It is used to access the 64kB of data memory.
The address and data range of devices with on-chip program and data memory overlap the 64k memory
space. When on-chip memory is enabled, accessing memory in the on-chip range will cause the device to
access internal memory. Memory accesses beyond the internal range will be addressed externally via
ports 0 and 2.
The ROMSIZE feature allows software to dynamically configure the maximum address of on-chip
program memory. This allows the device to act as a bootstrap loader for an external flash or NV SRAM.
Secondly, this method can also be used to increase the amount of available program memory from 64kB
to 80kB without bank switching (Section
6 ).
Program and data memory can also be increased beyond the 64kB limit using bank-switching techniques.
This is described in Application Note 81: Memory Expansion with the High-Speed Microcontroller
Family.
4.1.2 Register Map
The register map is illustrated in Figure 4-2 . It is entirely separate from the program and data memory
areas mentioned above. A separate class of instructions is used to access the registers. There are 256
potential register location values. In practice, the high-speed microcontroller has 256 bytes of Scratchpad
RAM and up to 128 special function registers (SFRs). This is possible since the upper 128 Scratchpad
RAM locations can only be accessed indirectly. That is, the contents of a Working Register (described
below) will designate the RAM location. Thus a direct reference to one of the upper 128 locations must
be an SFR access. Direct RAM is reached at locations 0 to 7Fh (0 to 127).