Maxim Integrated High-Speed Microcontroller - Manual (Page 51)

High-Speed Microcontroller User’s Guide
Rev: 062210 51 of 176
EWT
Bit 1
Enable Watchdog Timer Reset. This bit enables/disables the ability of the watchdog
timer to reset the device. This bit has no effect on the ability of the watchdog timer to
generate a watchdog interrupt. The watchdog timer mode select bits (
CKCON .7-6)
control the timeout period of the watchdog timer. Clearing this bit will disable the
ability of the watchdog timer to generate a reset, but have no affect on the timer itself, or
its ability to generate a watchdog timer interrupt. This bit can only be modified using a
Timed Access Procedure. The default power-on reset state of this bit is 0 on the
ROMless devices. If the device contains internal program memory, the default power-on
reset state of EWT is determined by the Watchdog Default POR State bit (WDPOR)
located in the System Control Byte or a mask option. This bit is unaffected by all other
resets.
0 = A timeout of the watchdog timer will not cause the device to reset.
1 = A timeout of the watchdog timer will cause the device to reset.
RWT
Bit 0 Reset Watchdog Timer. Setting this bit will reset the watchdog timer count. This bit
must be set using a Timed Access procedure before the watchdog timer expires, or a
watchdog timer reset and/or interrupt will be generated if enabled. The timeout period is
defined by the Watchdog Timer Mode Select bits (
CKCON .7-6). This bit will always be
0 when read.
4.2.43 Accumulator (A or ACC)
7 6 5 4 3 2 1 0
SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
ACC.7–ACC.0
Bits 7–0 Accumulator. This register serves as the accumulator for arithmetic operations. It is
functionally identical to the accumulator found in the 80C32.