Maxim Integrated High-Speed Microcontroller - Manual (Page 109)

High-Speed Microcontroller User’s Guide
Rev: 062210 109 of 176
9.6 Interrupt Latency
Interrupt response will require a varying amount of time depending on the state of the microcontroller
when the interrupt occurs. If the microcontroller is performing an ISR with equal or greater priority, the
new interrupt will not be invoked. In other cases, the response time depends on the current instruction.
The fastest possible response to an interrupt is 5 machine cycles. This includes one cycle for detecting the
interrupt and four cycles to perform the LCALL that is inherent in the interrupt request. The maximum
response time (if no other interrupt is in service) occurs if the microcontroller is performing an RETI
instruction, and then executes a MUL or DIV as the next instruction. From the time an interrupt source is
activated (not detected), the longest reaction time is 13 machine cycles. This includes 1 cycle to detect the
interrupt, 3 cycles to finish the RETI, 5 to perform the MUL or DIV, then 4 for the LCALL to the ISR.
The maximum latency of 13 machine cycles is 52 clocks (13 x 4). Note that the maximum interrupt
latency of an 8051 is 96 clocks (8 machine cycles at 12 clocks per machine cycle). The maximum latency
for the high-speed microcontroller at 25MHz is about 2μs. The use of power management modes can
further increase the interrupt latency.