11 timer 0 lsb (tl0), 12 timer 1 lsb (tl1), 13 timer 0 msb (th0) – Maxim Integrated High-Speed Microcontroller User Manual
Page 30: 14 timer 1 msb (th1), Timer mode control (tmod), Tl0.7, Tl1.7

High-Speed Microcontroller User’s Guide
Rev: 062210
30 of 176
4.2.11
Timer 0 LSB (TL0)
7 6 5 4 3 2 1 0
SFR 8Ah
TL0.7
TL0.6
TL0.5
TL0.4 TL0.3 TL0.2
TL0.1 TL0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
TL0.7–TL0.0
Bits 7–0
Timer 0 LSB. This register contains the least significant byte of Timer 0.
4.2.12
Timer 1 LSB (TL1)
7 6 5 4 3 2 1 0
SFR 8Bh
TL1.7
TL1.6
TL1.5
TL1.4 TL1.3 TL1.2
TL1.1 TL1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
TL1.7–TL1.0
Bits 7–0
Timer 1 LSB. This register contains the least significant byte of Timer 1.
4.2.13
Timer 0 MSB (TH0)
7 6 5 4 3 2 1 0
SFR 8Ch
TH0.7
TH0.6
TH0.5
TH0.4 TH0.3 TH0.2
TH0.1 TH0.0
RW-0
RW-0
RW-0
RW-0 RW-0 RW-0
RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
TH0.7–TH0.0
Bits 7–0
Timer 0 MSB. This register contains the most significant byte of Timer 0.
4.2.14
Timer 1 MSB (TH1)
7 6 5 4 3 2 1 0
SFR 8Dh
TH1.7
TH1.6
TH1.5
TH1.4 TH1.3 TH1.2
TH1.1 TH1.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
TH1.7–TH1.0
Bits 7–0
Timer 1 MSB. This register contains the most significant byte of Timer 1.