Maxim Integrated High-Speed Microcontroller - Manual (Page 39)

High-Speed Microcontroller User’s Guide
Rev: 062210 39 of 176
4.2.26 Interrupt Priority (IP)
7 6 5 4 3 2 1 0
SFR B8h — PS1 PT2 PS0 PT1 PX1 PT0 PX0
— RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
Bit 7 Reserved. Read data is indeterminate.
PS1
Bit 6 Serial Port 1 Interrupt. This bit controls the priority of the serial port 1 interrupt.
0 = Serial port 1 priority is determined by the natural priority order.
1 = Serial port 1 is a high priority interrupt.
PT2
Bit 5 Timer 2 Interrupt. This bit controls the priority of Timer 2 interrupt.
0 = Timer 2 is determined by the natural priority order.
1 = Timer 2 is a high priority interrupt.
PS0
Bit 4 Serial Port 0 Interrupt. This bit controls the priority of the serial port 0 interrupt.
0 = Serial port 0 priority is determined by the natural priority order.
1 = Serial port 0 is a high priority interrupt.
PT1
Bit 3 Timer 1 Interrupt. This bit controls the priority of Timer 1 interrupt.
0 = Timer 1 is determined by the natural priority order.
1 = Timer 1 is a high priority interrupt.
PX1
Bit 2 External Interrupt 1. This bit controls the priority of external interrupt 1.
0 = External interrupt 1 is determined by the natural priority order.
1 = External interrupt 1 is a high priority interrupt.
PT0
Bit 1 Timer 0 Interrupt. This bit controls the priority of Timer 0 interrupt.
0 = Timer 0 is determined by the natural priority order.
1 = Timer 0 is a high priority interrupt.
PX0
Bit 0 External Interrupt 0. This bit controls the priority of external interrupt 0.
0 = External interrupt 0 is determined by the natural priority order.
1 = External interrupt 0 is a high priority interrupt.
4.2.27 Slave Address Mask Enable Register 0 (SADEN0)
7 6 5 4 3 2 1 0
SFR B9h SADEN0.7 SADEN0.6 SADEN0.5 SADEN0.4 SADEN0.3 SADEN0.2 SADEN0.1 SADEN0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
SADEN0.7–
SADEN0.0
Bits 7–0 Slave Address Mask Enable Register 0. This register functions as a mask when
comparing serial port 0 addresses for automatic address recognition. When a bit in this
register is set, the corresponding bit location in the
SADDR0 register will be exactly
compared with the incoming serial port 0 data to determine if a receiver interrupt should
be generated. When a bit in this register is cleared, the corresponding bit in the
SADDR0 register becomes a don’t care and is not compared against the incoming data.
All incoming data will generate a receiver interrupt when this register is cleared.