Maxim Integrated High-Speed Microcontroller Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for High-Speed Microcontroller Maxim Integrated
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 176 |
| Size: | 3.58 MB |
Show table of contents
Document Outline
- 1. INTRODUCTION
- 2. ORDERING INFORMATION
- 3. ARCHITECTURE
- 3.1 ALU
- 3.2 Special Function Registers (SFRs)
- 3.2.1 Accumulator
- 3.2.2 B Register
- 3.2.3 Program Status Word
- 3.2.4 Data Pointer(s)
- 3.2.5 Stack Pointer
- 3.2.6 I/O Ports
- 3.2.7 Timer/Counters
- 3.2.8 UARTs
- 3.2.9 Scratchpad Registers (RAM)
- 3.2.10 Stack
- 3.2.11 Working Registers
- 3.2.12 Program Counter
- 3.2.13 Address/Data Bus
- 3.2.14 Watchdog Timer
- 3.2.15 Power Monitor
- 3.2.16 Interrupts
- 3.2.17 Timing Control
- 3.2.18 Real-Time Clock
- 3.2.19 Feature Summary
- 4. PROGRAMMING MODEL
- 4.1 Memory Organization
- 4.2 Special Function Registers
- 4.2.1 Port 0 (P0)
- 4.2.2 Stack Pointer (SP)
- 4.2.3 Data Pointer Low 0 (DPL)
- 4.2.4 Data Pointer High 0 (DPH)
- 4.2.5 Data Pointer Low 1 (DPL1)
- 4.2.6 Data Pointer High 1 (DPH1)
- 4.2.7 Data Pointer Select (DPS)
- 4.2.8 Power Control (PCON)
- 4.2.9 Timer/Counter Control (TCON)
- 4.2.10 Timer Mode Control (TMOD)
- 4.2.11 Timer 0 LSB (TL0)
- 4.2.12 Timer 1 LSB (TL1)
- 4.2.13 Timer 0 MSB (TH0)
- 4.2.14 Timer 1 MSB (TH1)
- 4.2.15 Clock Control (CKCON)
- 4.2.16 Port 1 (P1)
- 4.2.17 External Interrupt Flag (EXIF)
- 4.2.18 RTC Trim Register (TRIM)
- 4.2.19 Serial Port 0 Control (SCON0)
- 4.2.20 Serial Data Buffer 0 (SBUF0)
- 4.2.21 Port 2 (P2)
- 4.2.22 Interrupt Enable (IE)
- 4.2.23 Slave Address Register 0 (SADDR0)
- 4.2.24 Slave Address Register 1 (SADDR1)
- 4.2.25 Port 3 (P3)
- 4.2.26 Interrupt Priority (IP)
- 4.2.27 Slave Address Mask Enable Register 0 (SADEN0)
- 4.2.28 Slave Address Mask Enable Register 1 (SADEN1)
- 4.2.29 Serial Port Control (SCON1)
- 4.2.30 Serial Data Buffer 1 (SBUF1)
- 4.2.31 ROM Size Select (ROMSIZE)
- 4.2.32 Power Management Register (PMR)
- 4.2.33 Status Register (STATUS)
- 4.2.34 Timed Access Register (TA)
- 4.2.35 Timer 2 Control (T2CON)
- 4.2.36 Timer 2 Mode (T2MOD)
- 4.2.37 Timer 2 Capture LSB (RCAP2L)
- 4.2.38 Timer 2 Capture MSB (RCAP2H)
- 4.2.39 Timer 2 LSB (TL2)
- 4.2.40 Timer 2 MSB (TH2)
- 4.2.41 Program Status Word (PSW)
- 4.2.42 Watchdog Control (WDCON)
- 4.2.43 Accumulator (A or ACC)
- 4.2.44 Extended Interrupt Enable (EIE)
- 4.2.45 B Register (B)
- 4.2.46 Real-Time Alarm Subsecond Register (RTASS)
- 4.2.47 Real-Time Alarm Second Register (RTAS)
- 4.2.48 Real-Time Alarm Minute Register (RTAM)
- 4.2.49 Real-Time Alarm Hour Register (RTAH)
- 4.2.50 Extended Interrupt Priority (EIP)
- 4.2.51 Real-Time Clock Control Register (RTCC)
- 4.2.52 Real-Time Clock Subsecond Register (RTCSS)
- 4.2.53 Real-Time Clock Second Register (RTCS)
- 4.2.54 Real-Time Clock Minute Register (RTCM)
- 4.2.55 Real-Time Clock Hour Register (RTCH)
- 4.2.56 Real-Time Clock Day Register 0 (RTCD0)
- 4.2.57 Real-Time Clock Day Register 1 (RTCD1)
- 4.3 Instruction Timing
- 4.4 Addressing Modes
- 4.5 Program Status Flags
- 5. CPU TIMING
- 6. MEMORY ACCESS
- 7. POWER MANAGEMENT
- 8. RESET CONDITIONS
- 9. INTERRUPTS
- 10. PARALLEL I/O
- 11. PROGRAMMABLE TIMERS
- 12. SERIAL I/O
- 13. TIMED-ACCESS PROTECTION
- 14. REAL-TIME CLOCK
- 15. BATTERY BACKUP
- 16. INSTRUCTION SET DETAILS
- 17. TROUBLESHOOTING
- 18. MICROCONTROLLER DEVELOPMENT SUPPORT
- 18.1 Technical Support
- 18.2 Development Tools
- 18.3 Software Compatibility
- 18.4 High-Level Language Compilers
- 19. REVISION HISTORY