Maxim Integrated High-Speed Microcontroller - Manual (Page 132)

High-Speed Microcontroller User’s Guide
Rev: 062210 132 of 176
11.9 Watchdog Timer
The watchdog timer is a user-programmable clock counter that can serve as a time-base generator, an
event timer, or a system supervisor. As can be seen in the diagram of
Figure 11-8 , the main system clock
drives the timer that is supplied to a series of dividers. The divider output is selectable and determines the
interval between timeouts. When the timeout is reached, an interrupt flag will be set, and if enabled, a
reset will occur. The interrupt flag will cause an interrupt to occur if its individual enable bit is set and the
global interrupt enable is set. The reset and interrupt are completely discrete functions that may be
acknowledged or ignored, together or separately for various applications.
Figure 11-8. Watchdog Timer
The watchdog timer-reset function works as follows: After initializing the correct timeout interval
(discussed below), software first restarts the watchdog using RWT (
WDCON .0) and then enables the
reset mode by setting the enable watchdog timer reset (EWT = WDCON .1) bit. At any time prior to
reaching its user selected terminal value, software can set the reset watchdog timer (RWT = WDCON .0)
bit. If RWT is set before the timeout is reached, the timer will start over. If the timeout is reached without
RWT being set, the watchdog will reset the CPU. Hardware will automatically clear RWT after software
sets it. When the reset occurs, the watchdog timer reset flag (WTRF =
WDCON .2) will automatically be
set to indicate the cause of the reset, however software must clear this bit manually.
The watchdog timer is a free-running timer. When used as a simple timer with both the reset and interrupt
functions disabled (EWT = 0 and EWDI = 0), the timer will continue to set the watchdog interrupt flag
each time the timer completes the selected timer interval as programmed by WD1 (
CKCON .7) and WD0
DIVIDE BY
2
17
DIVIDE BY
2
3
DIVIDE BY
2
3
DIVIDE BY
2
3
RWT (WDCON.0
(Reset Watchdog)
WD1 (CKCON.7)
WD0 (CKCON.6)
TIMEOUT
XTAL1
XTAL2
DIVIDE BY
1/16/256
CLOCK DIVIDE CONTROL
CD1 CD0 DIVISOR
No PMR register 1
0 X 1
1 0 16
1 1 256
TIMEOUT
SELECTOR
WDIF
(WDCON.3)
EWDI (EIE.4)
(Enable Watchdog Interrupt)
WATCHDOG
INTERRUPT
RESET
WTRF
(WDCON.2)
512 CLOCK
DELAY
EWT (WDCON.1)
(Enable Watchdog Timer Reset)
2
17
2
20
2
23
2
26