Maxim Integrated High-Speed Microcontroller - Manual (Page 103)

High-Speed Microcontroller User’s Guide
Rev: 062210 103 of 176
8.1.3 External Reset
If the RST input is taken to a logic 1, the CPU is forced into a reset state. This does not occur
instantaneously, as the condition must be detected and then clocked into the microcontroller. It requires a
minimum of two machine cycles to detect and invoke the reset state. Thus the reset is a synchronous
operation and the crystal must be running to cause an external reset.
Once the reset state is invoked, it is maintained as long as RST = 1. When the RST is removed, the CPU
will exit the reset state within two machine cycles and begin execution at address 0000h. All registers
default to their power-on reset state. There is no flag to indicate that an external reset was applied.
However, since the other two sources have associated flags, the RST pin is the default source when
neither POR nor WTRF is set.
If a RST is applied while the processor is in the Stop mode, the scenario changes slightly. As mentioned
above, the reset is synchronous and requires a clock to be running. Since the Stop mode stops all clocks,
the RST will first cause the oscillator to begin running and force the program counter to 0000h. Rather
than a two-machine cycle delay as described above, the processor applies the full power-on delay (65,536
clocks) to allow the oscillator to stabilize.
8.2 Reset State
Regardless of the source of the reset, the state of the microcontroller is the same while in reset. When in
reset, the oscillator is running, but no program execution is allowed. When the reset source is external, the
user must remove the reset stimulus. When power is applied to the device, the power-on delay removes
the stimulus automatically.
Resets do not affect the Scratchpad RAM. Thus any data stored in RAM will be preserved. The contents
of internal MOVX data memory will also remain unaffected by a reset. Note that if the power supply dips
below approximately 2V, the RAM contents may be lost. The minimum voltage required for RAM data
retention in not specified. Since it is impossible to determine if the power was lower than 2V prior to the
power-on reset, RAM must be assumed lost when POR is set.
The reset state of SFR bits are described in Section
4 . Bits marked SPECIAL have conditions that can
affect their reset state. Consult the individual bit descriptions for more information. Note that the stack
pointer will also be reset. The stack is effectively lost during a reset even though the RAM contents are
not altered. Interrupts and timers are disabled. The state of the watchdog timer is dependent on the
specific device in use. Note that the watchdog timeout defaults to its shortest interval on any reset. I/O
Ports are taken to a weak high state (FFh). This leaves each port pin configured with the data latch set to a
1. Ports do not go to the 1 state instantly when a reset is applied, but will be taken high within two
machine cycles of asserting a reset. When the reset stimulus is removed, program execution begins at
address 0000h.
8.3 No-Battery Reset
The battery backup feature of the DS87C530 introduces a new type of reset condition. Most SFR bits are
automatically reset to their default state upon a power-on reset. The external backup battery feature makes
some bits non-volatile, however, and these battery-backed bits will not change state when a power-on
reset is applied. Upon the loss or initial connection of battery power these bits will default to the state
shown in
Table 8-A . Any bits not listed below are either unchanged or set to their default state by a
power-on reset.
Table 8-A. No-Battery Reset Default