Maxim Integrated High-Speed Microcontroller - Manual (Page 133)

High-Speed Microcontroller User’s Guide
Rev: 062210 133 of 176
( CKCON .6). Restarting the timer using the RWT ( WDCON .0) bit, allows software to use the timer in a
polled timeout mode. The WDIF bit is cleared by software or any reset.
The watchdog interrupt is also available for applications that do not need a true watchdog reset but simply
a very long timer. The interrupt is enabled using the enable watchdog timer interrupt (EWDI =
EIE .4) bit.
When the timeout occurs, the watchdog timer will set the WDIF bit ( WDCON .3), and an interrupt will
occur if the global interrupt enable (EA = IE.7) is set. Note that WDIF is set 512 clocks before a potential
watchdog reset. The watchdog interrupt flag will indicate the source of the interrupt, and must be cleared
by software.
Using the watchdog interrupt during software development can allow the user to select ideal watchdog
reset locations. Code is first developed without enabling the watchdog interrupt or reset functions. Once
the program is complete, the watchdog Interrupt function is enabled to identify the required locations in
code to set the RWT (
WDCON .0) bit. Incrementally adding instructions to reset the watchdog timer prior
to each address location (identified by the watchdog interrupt) will allow the code to eventually run
without receiving a watchdog interrupt. At this point the watchdog timer reset can be enabled without the
potential of generating unwanted resets. At the same time the watchdog interrupt may also be disabled.
Proper use of the watchdog interrupt with the watchdog reset allows interrupt software to survey the
system for errant conditions.
When using the watchdog timer as a system monitor, the watchdog-reset function should be used. If the
Interrupt function were used, the purpose of the watchdog would be defeated. For example, assume the
system is executing errant code prior to the watchdog interrupt. The interrupt would temporarily force the
system back into control by vectoring the CPU to the interrupt service routine. Restarting the watchdog
and exiting by an RETI or RET, would return the processor to the lost position prior to the interrupt. By
using the watchdog reset function, the processor is restarted from the beginning of the program, and
therefore placed into a known state.
The watchdog has four timeout selections based on the input crystal frequency as shown in the following
table. The selections are a preselected number of clocks. Therefore, the actual timeout interval is
dependent on the crystal frequency. Shown below are the four timeouts with some example periods for
different crystal speeds. Note that the time period shown is for the interrupt event. The reset, when
enabled, will occur 512 clocks later regardless of whether the interrupt is used. Therefore, the actual
watchdog timeout period is the number shown below plus 512 clocks. Watchdog-generated resets will
last for two machine cycles.
WD1 WD0
WATCHDOG
INTERVAL
NUMBER
OF
CLOCKS
TIME AT
1.8432MHz
(ms)
TIME AT
11.0592MHz
(ms)
TIME AT
16MHz
(ms)
TIME AT
20MHz
(ms)
TIME AT
25MHz
(ms)
0 0 2 17 131,072 71.11 11.85 8.19 6.55 5.24
0 1 2 20 1,048,576 568.89 94.81 65.54 52.43 41.94
1 0 2 23 8,388,608 4551.11 758.52 524.29 419.43 335.54
1 1 2 26 67,108,864 36408.88 6068.15 4194.30 3355.44 2684.35
The watchdog timeout selection is made using bits WD1 (
CKCON .7) and WD0 ( CKCON .6) as shown in
the table. The timeout selections possible are shown in the bit descriptions that follow. The watchdog
timeout period is affected by the use of power management modes. The slower clock rate, either divide-