Maxim Integrated High-Speed Microcontroller - Manual (Page 56)

High-Speed Microcontroller User’s Guide
Rev: 062210 56 of 176
1 = Reads of the RTC clock registers are permitted during a 1 ms window starting from
the time the bit is set. Immediately after setting this bit, software must wait 4 machine
cycles to allow all time registers to synchronize. The user should clear this bit when the
desired reads are complete, although it will clear automatically within 1.95ms if not
cleared in software.
RTCWE
Bit 2 RTC Write Enable. This bit temporarily halts the RTC to allow software to update the
current time. No loss of time will occur. This bit can only be modified using a Timed
Access procedure. Changing this bit from 1 to 0 will reset the
RTCSS register to 00h.
This bit will be cleared to 0 following any reset.
0 = Writes to the RTC clock registers (
RTCSS ;FAh, RTCS ;FBh, RTCM ;FCh,
RTCH ;FDh, RTCD0 ;FEh, RTCD1 ;FFh) are ignored. Attempts to set the RTCRE and
RTCWE bits simultaneously will be ignored. When this bit is cleared, software must
wait 4 machine cycles before setting either the RTCRE or RTCWE bit again.
1 = Writes to the RTC clock registers are permitted during a 1ms window starting from
the time this bit is set. Immediately after setting this bit, software must wait 4 machine
cycles to allow all time registers to synchronize. The user should clear this bit when the
desired updates are complete, although it will clear automatically after 1.95ms if not
cleared in software.
RTCIF
Bit 1 RTC Interrupt Flag. This bit indicates that a RTC alarm match has been made
between all the enabled alarm registers and their corresponding clock registers. This bit
will generate an RTC Interrupt if the ERTCI bit (
EIE .5) is set, and must be cleared by
software following an interrupt. Setting this bit cannot generate RTC interrupts.
Clearing all alarm compare enable bits (
RTCC .7-4) will also clear this bit. This bit will
be indeterminate following a no-battery reset, and is unaffected by all other resets. This
bit cannot be set in software.
0 = No RTC interrupts are pending.
1 = RTC Interrupt is pending/active.
RTCE
Bit 0 RTC Enable. This bit enables/disables the RTC oscillator, halting the RTC. This bit
must be accessed using a Timed-Access procedure. This bit will be indeterminate
following a no-battery reset, and is unaffected by all other resets. If RTC operation is
desired, it must be enabled following battery application.
0 = RTC oscillator is disabled.
1 = RTC oscillator is enabled.
4.2.52 Real-Time Clock Subsecond Register (RTCSS)
7 6 5 4 3 2 1 0
SFR FAh RTCSS.7 RTCSS.6 RTCSS.5 RTCSS.4 RTCSS.3 RTCSS.2 RTCSS.1 RTCSS.0
R*-* R*-* R*-* R*-* R*-* R*-* R*-* R*-*
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset, * = See Description
RTCSS.7–RTCSS.0
Bits 7–0 Real-Time Clock Subseconds. This register represents the subsecond value of the
RTC. It can be read only when the RTCRE bit is set, and writes are not permitted. It is
reset to 00h when the RTCWE bit is cleared. The register counts from 0h to FFh.