Maxim Integrated High-Speed Microcontroller - Manual (Page 89)

High-Speed Microcontroller User’s Guide
Rev: 062210 89 of 176
7.1.2 Power-Fail Reset
Devices that incorporate the power-fail reset will automatically invoke a reset when V
CC
drops below
V
RST
. This will halt device operation, and place all outputs in their reset state. This state will continue to
be held until V
CC
drops below the voltage necessary to power the port pins. Because V
RST
is lower than
V
PFW
, the microcontroller has the option to use the power-fail interrupt to place the device into a “safe”
state before the device halts operation with a power-fail reset. This feature is automatic on devices that
incorporate the power-fail reset feature, and cannot be disabled, except during Stop mode when the BGS
bit is 0.
7.1.3 Power-On Reset
When V
CC
is applied to a system using the high-speed microcontroller, the device will hold itself in reset
until power is within tolerance and stable. It requires no external circuits to accomplish this. As power
rises, the processor will stay in a reset state until V
CC
> V
RST
. As V
CC
rises above V
RST
, internal analog
circuits will detect this and activate the on-chip crystal oscillator. On-chip hardware will then count
65,536 oscillator clocks. During this count, V
CC
must remain above V
RST
or the process restarts. If an off-
chip clock source is used, clock counting still begins once V
CC
> V
RST
. This count period is used to make
certain that power is within tolerance, and that the oscillator has time to stabilize. This provides a very
controlled and predictable startup condition.
Once the 65,536 count period has elapsed, the reset condition is removed automatically, and software
execution will begin at the reset vector location of 0000h. Software will be able to detect the power-on
reset condition using the power-on reset (POR) flag. POR is located at
WDCON .6. This bit will be high
to indicate that a power-on reset has occurred. It should then be cleared by software.
The complete power cycle operation is shown in
Figure 7-1 . Note that the interrupt threshold is fixed, but
the interrupt itself is optional. Reset thresholds are also fixed and the reset operation is transparent. It
requires no external components and no action by software to control reset operation.
7.1.4 Bandgap Select
When present, the bandgap reference will provide a precise voltage reference for the power-fail monitor
circuitry. The bandgap is normally disabled automatically upon entering Stop mode to provide the lowest
power state. Since the bandgap is inactive, there can be no power-fail interrupt and no power-fail reset,
similar to a traditional 8051.
If the use of the power-fail features are desired in Stop mode, the BGS bit (
EXIF , 91h) may be used.
When set to a logic 1 by software, the bandgap reference and associated power monitor circuits will
remain active in Stop mode. The price of this feature is higher power supply current requirements.
BGS allows the user to decide whether the control circuitry and its associated power consumption are
needed. If the application is such that power will not fail while in Stop or if it does not matter that power-
fails, the BGS should be set to 0 (default). If power can fail at any time and cause problems, the BGS
should be set to 1.