Maxim Integrated High-Speed Microcontroller - Manual (Page 108)

High-Speed Microcontroller User’s Guide
Rev: 062210 108 of 176
9.3 Simulated Interrupts
Software can simulate any interrupt source by setting the corresponding flag bit. This forces an interrupt
condition that will be acknowledged if enabled and is otherwise indistinguishable from the real thing.
Thus an interrupt flag bit should never be set to a logic 1 by software inadvertently. Once an interrupt has
been acknowledged, software cannot prevent or end the interrupt by clearing its flag. However, if for
some reason the interrupt acknowledge is delayed, software may clear the flag and thereby prevent the
interrupt from occurring. One exception is the real-time clock interrupt flag, RTCIF, which cannot be set
in software.
9.4 Interrupt Priorities
The high-speed microcontroller has three interrupt priority levels: highest, high, and low.
The power-fail interrupt is the only source that has highest priority and this level is fixed. The remaining
sources are individually programmable to either high or low. Low priority is the default. A low priority
interrupt can be interrupted by a high (or highest) priority interrupt. A high priority interrupt can only be
interrupted by the power-fail interrupt.
When an interrupt occurs and is serviced, its priority determines if its ISR can be interrupted. No interrupt
source of equal or lesser priority can interrupt another source. That is, an incoming interrupt must be of a
higher priority than the one currently being serviced to have priority.
If two interrupt sources of equal priority levels are requested simultaneously, the natural priority is used
to arbitrate. The natural priority is given in
Table 9-A . Note that natural priority is only used to resolve
simultaneous requests. Once an interrupt of a given priority is invoked, only a source that is programmed
with a higher priority can intercede.
9.5 Interrupt Acknowledge Cycle
The process of acknowledging an interrupt requires multiple machine cycles that begin with the setting of
the associated flag. For edge-triggered external interrupts and internal interrupt sources, the interrupt flags
are set automatically by hardware. For level-sensitive external interrupts, the flags are actually under
control of the external signal, and the flag will rise and fall with the pin level. Each interrupt flag is
sampled once per machine cycle. Later in the same machine cycle, the samples are polled by hardware. If
the sample indicates a pending interrupt and the interrupt is enabled, then on the next machine cycle it
will be acknowledged by the hardware forcing an LCALL to the appropriate vector address. This LCALL
will occur unless blocked by one of the following conditions.
1) An interrupt of equal or greater priority has already been invoked and the RETI instruction has not
been issued to terminate it.
2) The current machine cycle is not the final cycle in the execution of the current instruction.
3) The instruction in progress is an RETI or a write to
IP , IE , EIP , or EIE .
The individual interrupt sources and associated enable and priority bits are shown in
Figure 9-1 . While
the final selection of the appropriate interrupt vector address is referred to as a polling process, this
function is actually performed in a single machine cycle using combinatorial logic.