Maxim Integrated High-Speed Microcontroller - Manual (Page 102)

High-Speed Microcontroller User’s Guide
Rev: 062210 102 of 176
8. RESET CONDITIONS
The high-speed microcontroller provides several ways to place the CPU in a reset state. It also offers the
means for software to determine the cause of a reset. The reset state of most processor bits is not
dependent on the type of reset, but selected bits do depend on the reset source. The reset sources and the
reset state are described below.
8.1 Reset Sources
High-speed microcontrollers have three ways of entering a reset state: power-on/power-fail reset,
watchdog timer reset, and external reset.
8.1.1 Power-On/Fail Reset
Members of the high-speed microcontroller family incorporate an internal voltage reference that holds the
CPU in the power-on reset state while V
CC
is out of tolerance. Once V
CC
rises above the threshold, the
microcontroller restarts the oscillation of the external crystal and count 65,536 clock cycles. The
processor will then begin software execution at location 0000h.
The voltage at which the reset state is entered depends on the specific device. If the device does not
contain a precision voltage reference, the power-on reset threshold may be anywhere between 0.8V and
V
CCMIN
. If the device incorporates a precision voltage reference, the threshold will be as specified by the
V
RST
parameter in the data sheet. This helps the system maintain reliable operation by only permitting
processor operation when voltage is in a know-good state.
The processor will exit the reset condition automatically once the above conditions are met. This happens
automatically, needing no external components or action. Execution begins at the standard reset vector
address of 0000h. Software can determine that a power-on reset has occurred using the power-on reset
flag (POR). It is located at
WDCON .6. Since all resets cause a vector to location 0000h, the POR flag
allows software to acknowledge that power-failure was the reason for a reset.
Software should clear the POR bit after reading it. When a reset occurs, software is able to determine if a
power cycle was the cause. In this way, processing may take a different course for each of the three resets
if applicable. When power-fails (drops below V
RST
), the power monitor invokes the reset state again. This
reset condition remains while power is below the threshold. When power returns above the reset
threshold, a full power-on reset is performed. A brownout that causes V
CC
to drop below V
RST
appears the
same as a power-up.
8.1.2 Watchdog Timer Reset
The watchdog timer is a free-running timer with a programmable interval. Software can clear the timer at
anytime, causing the interval to begin again. The watchdog supervises CPU operation by requiring
software to clear it before the timeout expires. If the timer is enabled and software fails to clear it before
this interval expires, the CPU is placed into a reset state. The reset state is maintained for two machine
cycles. Once the reset is removed, the software resumes execution at 0000h.
The watchdog timer is fully described in Section
11 . Software can determine that a watchdog timeout was
the reason for the reset by using the watchdog timer reset flag (WTRF). WTRF is located at WDCON .2.
Hardware sets this bit to a logic 1 when the watchdog times out without being cleared by software if
EWT = 1. If a watchdog timer reset occurs, software should clear this flag manually. This allows software
to detect the event if it occurs again.