Maxim Integrated High-Speed Microcontroller - Manual (Page 11)

High-Speed Microcontroller User’s Guide
Rev: 062210 11 of 176
3. ARCHITECTURE
The high-speed microcontroller is based on the industry-standard 80C52. The core is an accumulator-
based architecture using internal registers for data storage and peripheral control. It executes the standard
8051 instruction set. This section provides a brief description of each architecture feature. Details
concerning the programming model, instruction set, and register description are provided in Section
4 .
3.1 ALU
The ALU is responsible for math functions, comparisons, and general decision making in the high-speed
microcontroller. The ALU is not explicitly used by software. Instruction decoding prepares the ALU
automatically and passes it the appropriate data. The ALU primarily uses two special function registers
(SFRs) as the source and destination for all operations. These are the Accumulator and B registers. The
ALU also provides status information in the program status register. The SFRs are described below.
3.2 Special Function Registers (SFRs)
All peripherals and operations that are not explicit instructions in the high-speed microcontroller are
controlled through SFRs. All SFRs are described in Section
4 . The most commonly used registers that are
basic to the architecture are also described below.
3.2.1 Accumulator
The Accumulator is the primary register ( ACC ) used in the high-speed microcontroller. It is the source
and destination of most math, data movement, decisions, and other operations. Although it can be
bypassed, most high-speed instructions require the use of the accumulator (ACC) as one argument.
3.2.2 B Register
The B register ( B ) is used as the second 8-bit argument in multiply and divide operations. When not used
for these purposes, the B register can be used as a general-purpose register.
3.2.3 Program Status Word
The program status word holds a selection of bit flags that include the carry flag, auxiliary carry flag,
general purpose flag, register bank select, overflow flag, and parity flag.
3.2.4 Data Pointer(s)
The data pointer is used to designate a memory address for the MOVX instruction. This address can point
to a MOVX RAM location, either on- or off-chip, or a memory-mapped peripheral. When moving data
from one memory area to another or from memory to a memory-mapped peripheral, a pointer is needed
for both the source and destination. Thus, the high-speed microcontroller offers two data pointers. The
user selects the active pointer via a dedicated SFR bit.
3.2.5 Stack Pointer
The microcontroller provides a stack in the scratchpad RAM area. The stack pointer denotes the register
location at the top of the stack, which is the last used value. The user can place the stack anywhere in
scratchpad RAM by setting the stack pointer to that location.
3.2.6 I/O Ports
The standard high-speed microcontroller offers four 8-bit I/O ports. ROM less versions use Port 0 and
Port 2 as address and data buses. In those versions, only two ports are available for general-purpose I/O.
Each I/O port is a SFR that can be written or read. The I/O port has a latch that retains the value which
software writes. In general, during a read operation, software reads the state of the external pin. Each port
is represented by a SFR location.