Maxim Integrated High-Speed Microcontroller - Manual (Page 65)

High-Speed Microcontroller User’s Guide
Rev: 062210 65 of 176
Due to the limited number of edges within a machine cycle, selected events must occur between edges.
The high-speed microcontroller employs sophisticated circuits to create half and quarter clock events.
That is, some events occur between clock edges. Such circuits assure that events occur as precisely as if a
clock edge were available. While being generally transparent to the user, these circuits result in the use of
fractional clocks in the electrical specifications. For example, a time can be specified as 2.5t
CLCL
.
As mentioned above, a machine cycle is the basic timing unit of most functions in the high-speed
microcontroller. A machine cycle of the high-speed microcontroller is the time required to execute a
single cycle instruction. Almost half the op codes of the 8051 instruction set are implemented in a single
machine cycle in the high-speed microcontroller. The remaining instructions require multiple machine
cycles.
The power management modes implemented on some devices modify the number of clock cycles needed
to execute an instruction. Instead of 4 clocks per machine cycle, power management mode 1 (PMM1) and
power management mode 2 (PMM2) use 64 and 1024 clocks per cycle respectively to conserve power. A
full description of the power management modes and their effect on CPU operation is provided in
Section
7 .
All instructions are coded within an 8-bit field called an op code. This single byte must be fetched from
program memory. The CPU decodes the op code. It determines what action the microcontroller takes and
whether more information is needed from memory. If no other memory is needed, then only one byte was
required. Thus the instruction is called a one-byte instruction. In some cases, more data is needed. These
will be two- or three-byte instructions.
In most cases, the number of memory accesses (bytes) needed by an instruction is equal to the number of
machine cycles. Thus, single-cycle instructions contain one byte, and two-cycle instructions have two
bytes. This is true except for the special cases mentioned below.
5.6.1 Single-Cycle Instructions
The standard single-cycle instruction timing is shown in Figure 5-3 . As previously mentioned, there are
126 op codes that are single-cycle instructions. An example of a single-cycle instruction is as follows:
DEC A 14h
5.6.2 Two-Cycle Instructions
All two-cycle instructions require two cycles because they involve two bytes or require two memory
accesses. The first byte is an op code that instructs the CPU. This is the instruction itself. The second byte
is normally an operand or it specifies the location of the operand. For example, the instruction “ANL A,
direct” uses two cycles and requires two bytes. Two examples are as follows:
ANL A, direct
55h
a7-0
ANL A, #data
54h
d7-d0
Note that in the first example, the first memory access is the op code. The second memory access is the
location of the operand in the register map. Since the result is stored in an internal register, this operation
does not require a memory access. The second example is very similar. Again, the first byte represents the
op code. In this example, the second byte is the operand itself. This byte is used directly by the
instruction. The timing for a two-cycle instruction is shown in
Figure 5-4 .