Maxim Integrated High-Speed Microcontroller - Manual (Page 37)

High-Speed Microcontroller User’s Guide
Rev: 062210 37 of 176
4.2.22 Interrupt Enable (IE)
7 6 5 4 3 2 1 0
SFR A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
EA
Bit 7 Global Interrupt Enable. This bit controls the global masking of all interrupts except
power-fail interrupt, which is enabled by the EPFI bit (
WDCON .5).
0 = Disable all interrupt sources. This bit overrides individual interrupt mask settings.
1 = Enable all individual interrupt masks. Individual interrupts will occur if enabled.
ES1
Bit 6 Enable Serial Port 1 Interrupt. This bit controls the masking of the serial port 1 interrupt.
0 = Disable all serial port 1 interrupts.
1 = Enable interrupt requests generated by the RI_1 (
SCON1 .0) or TI_1 ( SCON1 .1) flags.
ET2
Bit 5 Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt.
0 = Disable all Timer 2 interrupts.
1 = Enable interrupt requests generated by the TF2 flag (
T2CON .7).
ES0
Bit 4 Enable Serial Port 0 Interrupt. This bit controls the masking of the serial port 0 interrupt.
0 = Disable all serial port 0 interrupts.
1 = Enable interrupt requests generated by the RI_0 (
SCON0 .0) or TI_0 ( SCON0 .1) flags.
ET1
Bit 3
Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
0 = Disable all Timer 1 interrupts.
1 = Enable all interrupt requests generated by the TF1 flag (
TCON .7).
EX1
Bit 2
Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
0 = Disable external interrupt 1.
1 = Enable all interrupt requests generated by the
INT1 pin.
ET0
Bit 1 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt.
0 = Disable all Timer 0 interrupts.
1 = Enable all interrupt requests generated by the TF0 flag (
TCON .5).
EX0
Bit 0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
0 = Disable external interrupt 0.
1 = Enable all interrupt requests generated by the
INT0 pin.
4.2.23 Slave Address Register 0 (SADDR0)
7 6 5 4 3 2 1 0
SFR A9h SADDR0.7 SADDR0.6 SADDR0.5 SADDR0.4 SADDR0.3 SADDR0.2 SADDR0.1 SADDR0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
SADDR0.7–
SADDR0.0
Bits 7–0 Slave Address Register 0. This register is programmed with the given or broadcast
address assigned to serial port 0.