Teledyne LeCroy Summit T28 PCIe Multi-lane Protocol Analyzer User Manual - Manual (Page 69)

Summit T28 PCI Express Multi‐Lane Protocol Analyzer User Manual 57
Link Settings Teledyne LeCroy
5.0 GT/s or 2.5 GT/s: When set to a specific speed, Teledyne LeCroy’s software forces the
hardware to record at that speed.
For Auto speed setting to work the polarity setting of lane 0 has to be correct. The
polarity can be set manually if the link is already in L0 state, or, for automatic polarity
detection, the bus has to go through a reset so the analyzer can track the polarity.
Note: Selecting Auto in the Speed drop‐down list will set the correct speed even if the analyzer does
not record a link training sequence.
5.14.2 Link Width
The Link Width sets the physical width of the link. Select the Link Width or select Auto
(see
Figure 5.1 on page 48 : 3B).
Note: Selecting Auto in the Link Width drop‐down list will find the correct link width even if the
analyzer does not record a link training sequence and for links that are in low power states.
5.14.3 Upstream and Downstream
Gives you low‐level control over each link direction. The heading for these boxes indicates
the port and/or unit to which the following options are applied based on the current
Analyzer configuration (see
Figure 5.1 on page 48 : 3C and 3D).
 Inhibit Channel: Do not record/upload this channel
 Reverse Lanes: Manual lane reversal. If Swizzling Config is set, the Reverse
Lanes will not work if Auto is checked.
 Invert Polarity
5.14.4 Reference Clock
If the PCI Express link under analysis uses spread‐spectrum clocking, then the Analyzer
must use the external reference clock from the system. If the Device Under Test does not
supply a reference clock, the internal reference clock in the Analyzer module can be used
instead (see
Figure 5.1 on page 48 : 3E). Only the standard PCIe reference clock is
supported.
5.14.5 SMA
For SMA clock, both inputs must be connected to a clock.
5.14.6 Disable Descrambling
If checked, causes the Analyzer to assume that none of the PCI Express traffic is
scrambled. By default, the Analyzer determines the scrambling state of the devices under
test (see
Figure 5.1 on page 48 : 3F).