Epson S1D13705 - Manual (Page 551)

Epson Research and Development Page 5
Vancouver Design Center
Interfacing to an 8-bit Processor S1D13705
Issue Date: 01/12/20 X27A-G-015-01
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4-1: Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4-2: Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of Figures
Figure 4-1: Typical Implementation of an 8-bit Processor to the S1D13705 Generic #2 Interface . . 11