2 clock input requirements, Figure 77: clock input requirements for clki, Table 77: clock input requirements for clki – Epson S1D13705 User Manual
Page 40: Clock input requirements, Table 7-7: clock input requirements for clki, Figure 7-7: clock input requirements for clki
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Epson Research and Development
Vancouver Design Center
S1D13705
Hardware Functional Specification
X27A-A-001-10
Issue Date: 02/02/01
7.2 Clock Input Requirements
Figure 7-7: Clock Input Requirements for CLKI
Note
When CLKI is > 25MHz the Input Clock Divide bit (REG[02h] bit 4) must be set to 1.
Table 7-7: Clock Input Requirements for CLKI
Symbol
Parameter
Min
Max
Units
f
CLKI
Input Clock Frequency (CLKI)
50
MHz
T
CLKI
Input Clock period (CLKI)
1/f
CLKI
ns
t
PWH
Input Clock Pulse Width High (CLKI)
8
ns
t
PWL
Input Clock Pulse Width Low (CLKI)
8
ns
t
f
Input Clock Fall Time (10% - 90%)
5
ns
t
r
Input Clock Rise Time (10% - 90%)
5
ns
t
PWL
t
PWH
t
f
Clock Input Waveform
tr
T
CLKI
V
IH
VIL
10%
90%