Epson S1D13705 - Manual (Page 55)

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Vancouver Design Center
Hardware Functional Specification S1D13705
Issue Date: 02/02/01 X27A-A-001-10
Figure 7-22: Dual Monochrome 8-Bit Panel A.C. Timing
1. Ts = pixel clock period
2. t1
min
= t3
min
- 9Ts
3. t3
min
= [(((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8) x 2]Ts
5. t6
min
= [((REG[08h] bits 4-0) x 2)x 8 + 20]Ts
6. t7
min
= [((REG[08h] bits 4-0) x 2)x 8 + 29]Ts
Table 7-16: Dual Monochrome 8-Bit Panel A.C. Timing
Symbol Parameter Min Typ Max Units
t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)
t2 Frame Pulse hold from Line Pulse falling edge 9 Ts
t3 Line Pulse period note 3
t4 Line Pulse pulse width 9 Ts
t5 MOD delay from Line Pulse falling edge 1 Ts
t6 Shift Pulse falling edge to Line Pulse rising edge note 5
t7 Shift Pulse falling edge to Line Pulse falling edge note 6
t8 Line Pulse falling edge to Shift Pulse falling edge t14 + 2 Ts
t9 Shift Pulse period 8 Ts
t10 Shift Pulse pulse width low 4 Ts
t11 Shift Pulse pulse width high 4 Ts
t12 FPDAT[7:0] setup to Shift Pulse falling edge 4 Ts
t13 FPDAT[7:0] hold to Shift Pulse falling edge 4 Ts
t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts
t14 t10 t11
t12 t13
Data Timing
Frame Pulse
t1 t2
t3
t5
t4
Line Pulse
DRDY (MOD)
Sync Timing
Line Pulse
Shift Pulse
t8 t9
1 2
t7
t6
FPDAT[7:0]
Note: For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1