Epson S1D13705 - Manual (Page 508)

Page 14 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the Philips MIPS PR31500/PR31700 Processor
X27A-G-012-02 Issue Date: 01/02/13
4.3 S1D13705 Configuration and Pin Mapping
The S1D13705 is configured at power up by latching the state of the CNF[3:0] pins. Pin
BS# also plays a role in host bus interface configuration. For details on configuration, refer
to the S1D13705 Hardware Functional Specification, document number X27A-A-001-xx.
The table below shows those configuration settings relevant to the direct connection
approach.
Table 4-1: S1D13705 Configuration for Direct Connection
S1D13705
Configuration
Pin
Value hard wired on this pin is used to configure:
1 (IO V
DD
) 0 (V
SS
)
BS# Generic #2 Generic #1
CNF3 Big Endian Little Endian
CNF[2:0] 111: Generic #1 or #2
= configuration for Philips PR31500/PR31700 host bus interface