Epson S1D13705 - Manual (Page 537)

Epson Research and Development Page 9
Vancouver Design Center
Interfacing to the NEC VR4181A™ Microprocessor S1D13705
Issue Date: 01/02/13 X27A-G-013-02
2.1.2 LCD Memory Access Signals
The S1D13705 requires an addressing range of 128Kbytes. When the VR4181A’s external
LCD controller chip select signal is programmed to a window of that size, the S1D13705
must reside in the VR4181A physical address range of 133E 0000h to 133F FFFFh which
is part of the external ISA memory space.
The signals required for external LCD controller access are listed below and obey ISA
signalling rules.
• A[16:0] Address bus
• #UBE High byte enable (active low)
• #LCDCS LCD controller (S1D13705) chip select (active low)
• D[15:0] Data bus
• #MEMRD Read command (active low)
• #MEMWR Write command (active low)
• #MEMCS16 Sixteen-bit peripheral capability acknowledge (active low)
• IORDY Ready signal from S1D13705
• SYSCLK Optional, prescalable bus clock
Once an address in the LCD block of memory is accessed, the LCD chip select #LCDCS is
driven low. The read or write enable signals, #MEMRD or #MEMWR, are driven low for
the appropriate cycle and IORDY is driven low by the S1D13705 to insert wait states into
the cycle. The high byte enable is driven low for 16-bit transfers and high for 8-bit transfers.