Epson S1D13705 - Manual (Page 298)

Page 10 Epson Research and Development
Vancouver Design Center
S1D13705 S5U13705B00C Rev. 1.0 ISA Bus Evaluation Board User Manual
X27A-G-005-03 Issue Date: 01/02/13
3 LCD Interface Pin Mapping
Note
1. Un-used GPIO pins must be connected to IO V
DD
.
2. Inverse Video is enabled on FPDAT11 by REG[02h] bit 1.
Table 3-1: LCD Signal Connector (J5) Pinout
Connector Single Passive Panel Dual Passive Panel
Color TFT/D-TFD
Pin Name Pin #
Color Mono Color Mono
4-bit 8-bit
8-bit
Alternate
Format
4-bit 8-bit 8-bit 8-bit 9-bit 12-bit
BFPDAT0 1 driven 0 D0 LD0 driven 0 D0 D0 LD0 R2 R3
BFPDAT1 3 driven 0 D1 LD1 driven 0 D1 D1 LD1 R1 R2
BFPDAT2 5 driven 0 D2 LD2 driven 0 D2 D2 LD2 R0 R1
BFPDAT3 7 driven 0 D3 LD3 driven 0 D3 D3 LD3 G2 G3
BFPDAT4 9 D0 D4 UD0 D0 D4 D4 UD0 G1 G2
BFPDAT5 11 D1 D5 UD1 D1 D5 D5 UD1 G0 G1
BFPDAT6 13 D2 D6 UD2 D2 D6 D6 UD2 B2 B3
BFPDAT7 15 D3 D7 UD3 D3 D7 D7 UD3 B1 B2
BFPDAT8 17 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 B0 B1
BFPDAT9 19 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 R0
BFPDAT10 21 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 G0
BFPDAT11 23
GPIO4/
Inverse
Video
GPIO4/
Inverse
Video
GPIO4/
Inverse
Video
GPIO4/
Inverse
Video
GPIO4/
Inverse
Video
GPIO4/
Inverse
Video
GPIO4/
Inverse
Video
GPIO4 B0
BFPSHIFT 33 FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT
BFPSHIFT2 35 FPSHIFT2
BFPLINE 37 FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE
BFPFRAME 39 FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME
GND
2-26
(Even
Pins)
GND GND GND GND GND GND GND GND GND
N / C 28
VLCD 30 LCD panel negative bias voltage (-24V to -14V)
LCDVCC 32 +3.3V or +5V (selectable with JP4)
+12V 34 +12V +12V +12V +12V +12V +12V +12V +12V +12V
VDDH 36 LCD panel positive bias voltage (+23V to +40V)
BDRDY 38 MOD MOD MOD MOD MOD MOD DRDY DRDY
BLCDPWR 40 LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR