6 generic #2 interface timing, Figure 76: generic #2 timing, Table 76: generic #2 timing – Epson S1D13705 User Manual
Page 39: Generic #2 interface timing, Table 7-6: generic #2 timing, Figure 7-6: generic #2 timing
Epson Research and Development
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Vancouver Design Center
Hardware Functional Specification
S1D13705
Issue Date: 02/02/01
X27A-A-001-10
7.1.6 Generic #2 Interface Timing
Figure 7-6: Generic #2 Timing
Note
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 84
Table 7-6: Generic #2 Timing
Symbol
Parameter
Min
Max
Units
f
BCLK
Bus Clock frequency
50
MHz
T
BCLK
Bus Clock period
1/f
BCLK
t1
A[16:0], BHE#, CS# valid to WE#, RD# low
0
ns
t2
WE#, RD# high to A[16:0], BHE#,
CS# invalid
0
ns
t3
WE# low to D[15:0] valid (write cycle)
T
BCLK
t4
WE# high to D[15:0] invalid (write cycle)
0
ns
t5
RD# low to D[15:0] driven (read cycle)
16
ns
t6
D[15:0] valid to WAIT# high (read cycle)
0
ns
t7
RD# high to D[15:0] high impedance (read cycle)
10
ns
t8
WE#, RD# low to WAIT# driven low
14
ns
t9
BCLK to WAIT# high
10
ns
t10
WE#, RD# high to WAIT# high impedance
11
ns
t11
WAIT# high to WE#, RD# high
1T
BCLK
t8
t4
t9
t3
t1
t10
BCLK
A[16:0]
CS#
WE#,RD#
WAIT#
VALID
t2
Hi-Z
Hi-Z
Hi-Z
VALID
T
BCLK
t6
t7
VALID
Hi-Z
Hi-Z
D[15:0]
D[15:0]
t5
BHE#
(write)
(read)
t11