Epson S1D13705 - Manual (Page 540)

Page 12 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the NEC VR4181A™ Microprocessor
X27A-G-013-02 Issue Date: 01/02/13
4 VR4181A to S1D13705 Interface
4.1 Hardware Description
The NEC VR4181A microprocessor is specifically designed to support an external LCD
controller by providing the internal address decoding and control signals necessary. By
using the Generic # 2 interface, a glueless interface is achieved. The diagram below shows
a typical implementation of the VR4181A to S1D13705 interface.
Figure 4-1: Typical Implementation of VR4181A to S1D13705 Interface
WE1#
WE0#
DB[15:0]
WAIT#
RD#
BCLK
S1D13705
CS#
RESET#
AB[15:0]
#UBE
#MEMWR
D[15:0]
#LCDCS
#MEMRD
IORDY
A[16:0]
NEC VR4181A
Pull-up
BS#
RD/WR#
Vcc
Vcc
System RESET
Oscillator
#MEMCS16
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).