Epson S1D13705 - Manual (Page 46)

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S1D13705 Hardware Functional Specification
X27A-A-001-10 Issue Date: 02/02/01
7.3.4 Single Monochrome 8-Bit Panel Timing
Figure 7-13: Single Monochrome 8-Bit Panel Timing
VDP = Vertical Display Period = (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
VNDP = Vertical Non-Display Period = REG[0Ah] bits 5-0 Lines
HDP = Horizontal Display Period = ((REG[04h] bits 6-0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period = (REG[08h] + 4) x 8Ts
HNDP
VDP
FPLINE
FPSHIFT
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480
FPFRAME
LINE1 LINE2
FPLINE
DRDY (MOD)
1-2 1-10 1-634
1-3 1-11 1-635
1-4 1-12 1-636
1-5 1-13 1-637
1-6 1-14 1-638
1-7 1-15 1-639
1-8 1-16 1-640
1-1 1-9 1-633
DRDY (MOD)
VNDP
HDP
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
FPDAT[7:0]
FPDAT6
FPDAT5
FPDAT4
FPDAT7
FPDAT2
FPDAT1
FPDAT0
FPDAT3
For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1