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5 host bus interface pin mapping, Table 51: host bus interface pin mapping – Epson S1D13705 User Manual

Page 301

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Epson Research and Development

Page 13

Vancouver Design Center

S5U13705B00C Rev. 1.0 ISA Bus Evaluation Board User Manual

S1D13705

Issue Date: 01/02/13

X27A-G-005-03

5 Host Bus Interface Pin Mapping

Table 5-1: Host Bus Interface Pin Mapping

S1D13705

Pin Names

SH-3

SH-4

MC68K #1

MC68K #2

Generic Bus #1 Generic Bus #2

AB[16:1]

A[16:1]

A[16:1]

A[16:1]

A[16:1]

A[16:1]

A[16:1]

AB0

A0

A0

LDS#

A0

A0

A0

DB[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

D[15:0]

WE1#

WE1#

WE1#

UDS#

DS#

WE1#

BHE#

CS#

CSn#

CSn#

External Decode External Decode External Decode External Decode

BCLK

CKIO

CKIO

BCLK

BCLK

BCLK

BCLK

BS#

BS#

BS#

AS#

AS#

Connect to V

SS

Connect to IO V

DD

RD/WR#

RD/WR#

RD/WR#

R/W#

R/W#

RD1#

Connect to IO V

DD

RD#

RD#

RD#

Connect to IO V

DD

SIZ1

RD0#

RD#

WE0#

WE0#

WE0#

Connect to IO V

DD

SIZ0

WE0#

WE#

WAIT#

WAIT#

RDY#

DTACK#

DSACK1#

WAIT#

WAIT#

RESET#

RESET#

RESET#

RESET#

RESET#

RESET#

RESET#