3 clock input, 4 miscellaneous, 5 power supply – Epson S1D13705 User Manual
Page 27: Clock input, Miscellaneous, Power supply
Epson Research and Development
Page 21
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Hardware Functional Specification
S1D13705
Issue Date: 02/02/01
X27A-A-001-10
5.2.3 Clock Input
5.2.4 Miscellaneous
5.2.5 Power Supply
FPLINE
O
38
CN3
0
Line Pulse
FPSHIFT
O
28
CN3
0
Shift Clock
LCDPWR
O
43
CO1
0
Active high LCD Power Control
DRDY
O
42
CN3
0
This pin has multiple functions.
• TFT/D-TFD Display Enable (DRDY).
• LCD Backplane Bias (MOD).
• Second Shift Clock (FPSHIFT2).
See Table 5-3: “LCD Interface Pin Mapping,” on page 23
for
summary.
Pin Name
Type
Pin #
Driver
Description
CLKI
I
51
C
Input Clock
Pin Name
Type
Pin #
Cell
RESET#
State
Description
CNF[3:0]
I
46, 47,
48, 49
C
As set by
hardware
These inputs are used to configure the S1D13705 - see Table
5-1: “Summary of Power On/Reset Options,” on page 22.
Must be connected directly to IO V
DD
or V
SS
.
GPIO0
IO,
I
22
CS/
TS1
Input
This pin has multiple functions - see REG[03h] bit 2.
• General Purpose Input/Output pin.
• Hardware Power Save.
TESTEN
I
44
TEST
pulled low
Test Enable input. This input must be connected to V
SS
.
Pin Name
Type
Pin #
Driver
Description
COREVDD
P
1, 21, 41,
61
P
Core V
DD
IOVDD
P
10, 29, 52
P
IO V
DD
VSS
P
20, 27, 40,
50, 60, 72,
80
P
Common V
SS
Pin Name
Type
Pin #
Cell
RESET#
State
Description