Epson S1D13705 - Manual (Page 472)

Page 20 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the Motorola MPC821 Microprocessor
X27A-G-010-02 Issue Date: 01/02/13
4.5 Test Software
The test software to exercise this interface is very simple. It configures chip select 4 on the
MPC821 to map the S1D13705 to an unused 128k byte block of address space and loads
the appropriate values into the option register for CS4. At that point the software runs in a
tight loop reading the 13705 Revision Code Register REG[00h], which allows monitoring
of the bus timing on a logic analyzer.
The source code for this test routine is as follows:
BR4 equ $120 ; CS4 base register
OR4 equ $124 ; CS4 option register
MemStart equ $40 ; upper word of S1D13705 start address
RevCodeReg equ 1FFE0 ; address of Revision Code Register
Start mfspr r1,IMMR ; get base address of internal registers
andis. r1,r1,$ffff ; clear lower 16 bits to 0
andis. r2,r0,0 ; clear r2
oris r2,r2,MemStart ; write base address
ori r2,r2,$0801 ; port size 16 bits; select GPCM; enable
stw r2,BR4(r1) ; write value to base register
andis. r2,r0,0 ; clear r2
oris r2,r2,$ffc0 ; address mask – use upper 10 bits
ori r2,r2,$0708 ; normal CS negation; delay CS ½ clock;
; inhibit burst
stw r2,OR4(r1) ; write to option register
andis. r1,r0,0 ; clear r1
oris r1,r1,MemStart ; point r1 to start of S1D13705 mem space
Loop lbz r0,RevCodeReg(r1) ; read revision code into r1
b Loop ; branch forever
end