Echelon Series 6000 Chip databook - Manual (Page 8)

Table of Contents
Welcome ......................................................................................................... iii
Audience ........................................................................................................ iii
What’s New for Echelon’s Smart Transceivers and Neuron Chips ........... iii
Related Documentation ................................................................................ iv
Standards Documents Referenced in this Manual ..................................... vi
Introduction ....................................................................................................... 1
Product Family Overview .............................................................................. 2
FT 6000 Smart Transceiver .................................................................... 2
Neuron 6000 Processor ............................................................................ 2
Development Resources for Series 6000 Chips ............................................ 2
Introduction to L ON W ORKS Networks .......................................................... 3
Overview of the IzoT Platform ...................................................................... 4
Overview of Free Topology Technology ........................................................ 5
Key Features of Series 6000 Chips ............................................................... 8
Additional Key Features for FT 6000 Smart Transceivers................... 8
Specification Summaries ............................................................................... 9
Specification Summary for FT 6000 Smart Transceivers ..................... 9
Specification Summary for Neuron 6000 Processors .......................... 11
Hardware Resources ...................................................................................... 13
Series 6000 Architecture ............................................................................. 14
Neuron Processor Architecture ............................................................. 15
Multiple Processors ............................................................................... 17
Interrupts ............................................................................................... 19
Assembly Instruction Set ...................................................................... 19
Memory Architecture ................................................................................... 23
On-Chip Memory ................................................................................... 24
Memory Map .......................................................................................... 24
External Serial Memory Interface ........................................................ 26
Serial Peripheral Interface (SPI) ................................................... 26
Non-Volatile Memory Integrity ...................................................... 27
Device Support ................................................................................ 28
Device Programming....................................................................... 29
Recovering a Device ........................................................................ 29
Transience .............................................................................................. 30
Data Logging .......................................................................................... 30
Boot Loader ............................................................................................ 30
JTAG Interface ............................................................................................. 31
Operating Conditions ................................................................................... 32
Pin Assignments .......................................................................................... 34
FT 6000 Smart Transceiver .................................................................. 34
Neuron 6000 Processor .......................................................................... 36
Pin Connections ............................................................................................ 39
Characteristics of the Digital Pins .............................................................. 43
Communications Port (CP) Pins for the Neuron 6000 Processor .............. 44
Single-Ended Mode ................................................................................ 46
Collision Detection for Single-Ended Mode ................................... 48
Beta 1 and Beta 2 Timeslots in Single-Ended Mode .................... 48
Special-Purpose Mode ........................................................................... 50
Network Connection .................................................................................... 54
Connection for an FT 6000 Smart Transceiver ................................... 54
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