Echelon Series 6000 Chip databook - Manual (Page 20)

Key Features of Series 6000 Chips
Series 6000 chips include the following key features:
• Provide a high performance Neuron Core, with internal system clock rates up to 80
MHz
• Require as little as 30 mW of power for operations
• Packaged as a 7 mm by 7 mm 48-pin quad flat no leads (QFN) chip
• Include a serial memory interface for inexpensive external flash non-volatile memory
• Support up to 254 network variables (NVs) for FT 6000 Smart Transceivers and
Neuron 6000 Processors, without the need for a host microprocessor
• Support user-programmable interrupts to provide fast response time to external
events
• Provide an interface for the Institute of Electrical and Electronics Engineers (IEEE)
Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-1990) of
the Joint Test Action Group (JTAG) to allow a Series 6000 chip to be included in the
boundary-scan chain for device production tests
• Include 12 I/O pins with 35 programmable standard I/O models that support both 5 V
and 3.3 V I/O operation
• Support up to 256 KB of user application code space (with a 1MB external flash)
• Include 64 KB RAM (of which 44 KB is user accessible) and 16 KB of ROM on-chip
• Include a unique 48-bit MAC ID in every device for network installation and
management
• Support a –40°C to +85°C operating temperature range
• Compliant with the European Union Restriction of Hazardous Substances (RoHS)
Directive 2002/95/EC.
Additional Key Features for FT 6000 Smart
Transceivers
FT 6000 Smart Transceivers include the following additional key features:
• Support polarity insensitive free topology star, daisy chain, bus, loop, or mixed
topology wiring for TP/FT-10 channels
• Compliant with TP/FT-10 channels that currently use FT 3120 Smart Transceivers,
FT 3150 Smart Transceivers, FTT-10A transceivers, LPT-11 transceivers or FT-5000
Transceivers
• Provide very high common-mode noise immunity
8 Introduction