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Echelon Series 6000 Chip databook User Manual

Page 122

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source and sink capability. If your I/O circuitry has higher current requirements, you can

add external driver circuitry (for example, using a Fairchild Semiconductor

®

74AC245/74ACT245 Octal Bidirectional Transceiver or 74VHC245/74VHCT245 Octal

Buffer/Line Driver).
In addition, the Series 6000 device pins are all 3.3 V pins: the input pins are 5 V tolerant,

and the output pins are CMOS compatible. Series 3100 device pins are all 5 V pins.
For Series 3100, Series 5000, and Series 6000 devices, pins IO0 – IO7 have low-level detect

latches.
Because the I/O pins are controlled by system firmware, the timing for reading or writing an

I/O pin includes latency that can vary by I/O model and even vary by I/O pin. All inputs are

software sampled during processing for the Neuron C when statement. In general, the

latency scales inversely with the system clock rate.
To maintain and provide consistent behavior for external events, and to prevent setup and

hold metastability, all I/O pins, when configured as simple inputs, are passed through a

hardware synchronization block, shown in Figure 45, that is sampled by the internal system

clock.

D

Q

D

Q

IO0-IO11 Inputs

Internal System Clock

Synchronized

IO0-IO11 Inputs

I/O Input Synchronizer

Structure

Figure 45. Synchronization Block

I/O pins used for other functions do not have this synchronization requirement.
For Series 6000 devices, the sample rate is equivalent to the system clock rate. For a signal

to be reliably synchronized with an 80 MHz system clock, it must be at least 17.5 ns in

duration; see Figure 46.

80 MHz

System Clock

IO0-IO11 Inputs

(17.5 ns pulse)

t

setup

5 ns

t

hold

0 ns

Figure 46. Synchronization of External Signals for Series 6000 Devices

Any event that lasts longer than 220 ns (for a Series 3100 device at 10 MHz) or 17.5 ns (for a

Series 6000 device at 80 MHz) is synchronized by hardware, but there can be latency in

software sampling, which can result in a delay in detecting the event. If the state changes at

a faster rate than software sampling can process, the interim changes are not detected.
The following exceptions apply to the use of the synchronization block:

The chip select (CS~) input used in the slave B mode of the parallel I/O object

recognizes rising edges asynchronously.

The leveldetect input is latched by a flip-flop with a 200 ns clock (for Series 3100

devices) or a 12.5 ns clock (for Series 6000 devices). The level detect transition event

is latched, but there is a delay in software detection.

The SCI (UART) and SPI objects are buffered on byte boundaries by the hardware,

and are transferred to memory using an interrupt.

110

Input/Output Interfaces for the Series 6000