Echelon Series 6000 Chip databook - Manual (Page 58)

output after transmitting the last bit. The line-code violation begins after the end of the last
CRC bit, and lasts for at least 2.5 bit times. The last bit does not have a trailing clock edge.
The Transmit Enable pin is held active until the end of the line-code violation, and is then
released.
Differential Manchester coding is polarity-insensitive. Thus, reversal of polarity in the
communication link does not affect data reception.
A Neuron Chip in single-ended mode supports any of the following network bit rates:
• 2.5 Mbps
• 1.25 Mbps
• 625 kbps
• 312.5 kbps
• 156 kbps
• 78 kbps
• 39 kbps
• 19.5 kbps
• 9.6 kbps
• 4.8 kbps
The 625 kbps and lower bit rates are available for any of the system-clock rates of the
Neuron 6000 Processor. The 2.5 Mbps bit rate requires the Neuron 6000 Processor’s system
clock to be set at 40 MHz or higher, and the 1.25 Mbps bit rate requires the clock to be set to
20 MHz or higher.
Single-Ended Mode
Single-ended mode (3.3 V) is most commonly used with external active transceivers that
interface to media such as RF, IR, fiber optics, twisted-pair cable, and coaxial cable. Figure
16 shows the communications port configuration for single-ended mode operation. Data
communication occurs through the single-ended (with respect to GND) input and output
buffers on pins CP0 and CP1.
46 Hardware Resources