Interrupts, Assembly instruction set – Echelon Series 6000 Chip databook User Manual

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Interrupts

The Series 6000 architecture provides hardware support for handling three types of

interrupts:

•

Lowest priority: application interrupts

•

Medium priority: system interrupts

•

Highest priority: system-level traps

Application interrupts are asynchronous events related to I/O objects within an application

program. An application uses the Neuron C interrupt() clause to define the interrupt

condition and the interrupt task that handles the condition. The Neuron C program runs the

interrupt task whenever the interrupt condition is met. See the Neuron C Programmer’s

Guide for more information about writing interrupt tasks and handling interrupts.
System interrupts are asynchronous system events, such as communications events or SPI

UART events. These interrupts are handled by the system firmware.
System-level traps are also system events, generally error conditions. See Processor Integrity

for more information about these conditions.
For system clock rates of 20 MHz and higher, interrupts are handled by an independent

logical processor within the Neuron Core. At the two lower system clock rates, interrupts are

handled by the application processor. Thus, at the higher clock rates, an interrupt handler

runs in parallel with the application processor, and so does not affect the application

processor’s registers and stack space. At lower clock rates, an interrupt causes a context

switch within the application processor, that is, the interrupt handler saves the processor’s

registers before it runs and restores them after it completes. Thus, the current instruction

always completes prior to servicing a new interrupt. Such context switches also occur within

the ISR processor when higher priority interrupts require service.
Thus, when interrupts are processed within the ISR processor, application performance is

not degraded, but when interrupts are processed within the APP processor, application

performance can be affected because the one processor handles both the application and the

interrupts.

Assembly Instruction Set

Table 8, Table 9, and Table 10 list the processor instructions, their sizes (in bytes), and

their timings (in processor cycles). This information is provided to help you calculate code

sizes and execution times.
Most assembly instructions take between one and seven processor cycles (two instructions

require 14 cycles). Execution time scales inversely with the system clock rate. The formula

for instruction time is:

(

)

SystemCloc

cles

NumberOfCy

nTime

Instructio

For example, at a system clock rate of 80 MHz, instruction times vary between 37.5 ns and

175 ns.
Programming for a Neuron Chip or Smart Transceiver uses the Neuron C programming

language with the IzoT NodeBuilder Development Tool. Additional functions can be written

Series 6000 Chip Data Book